Antifuse based on silicided polysilicon bipolar transistor

ABSTRACT

An improved antifuse which employs the base-emitter junction of a silicided single polysilicon bipolar transistor. The distance between the base metal and emitter metal is shortened and results from self aligning process steps rather than lithographic steps, resulting in a lower and better controlled programming voltage, programming energy and ON state resistance. Typically the conductive filament formed in the new antifuse is about 0.65 microns long and is formed by a voltage pulse having a relatively slow rise time (e.g. 150 microseconds), resulting in improved properties which provide advantages in circuit design and in manufacturing circuits using the new antifuse.

This application is a 371 of PCT/CA98/00114 filed Feb. 13, 1998 and aCIP of Ser. No. 08/820,475 filed Mar. 17, 1997 now U.S. Pat. No.5,920,771.

FIELD OF THE INVENTION

This invention relates to programmable antifuses and to methods ofmaking the same.

BACKGROUND OF THE INVENTION

Antifuses have been known for some time and are disclosed for example inU.S. Pat. Nos. 3,191,151; 3,742,592; 5,019,878; and 5,298,784. Antifusesare devices which have a high impedance before programming and a lowimpedance after programming, and are used widely in integrated circuitstructures. An antifuse is the converse of a fuse, which can be employedin a similar manner. Use of an antifuse permits the tuning of variousanalog circuit parameters, the programming of digital logic, and theselection of certain pieces of redundant circuitry. An exemplaryapplication for antifuses (given by way of example only) is to switchdesired resistances into a voltage controlled oscillator (VCO), so thatthe center frequency and range of the VCO will be within desiredspecifications.

Antifuses can be formed from transistor or diode structures whichnormally have a high impedance when reverse biased. The appropriate PNjunction of the device can be shorted by applying a large reverse bias,causing part of the junction to melt and causing the metal whichcontacts the junction to flow into the molten region, thereby creating alow impedance metal filament.

Conventional antifuse structures typically require a relatively highprogramming voltage and energy, which may cause damage to the remainderof the integrated circuit in which the antifuse is located. It istherefore an object of the invention to provide an improved antifusestructure, and a method of forming an antifuse, which require a lowerprogramming voltage and energy than have typically been the case in thepast.

BRIEF SUMMARY OF THE INVENTION

Accordingly, in one of its aspects the invention provides a method ofmaking an antifuse in a silicided single polysilicon bipolar transistor,said transistor comprising:

(i) a collector layer,

(ii) a base layer overlying said collector layer and having an uppersurface,

(iii) an emitter structure overlying said base layer, said emitterstructure projecting above said base layer and having a sidewallextending above said base layer, said emitter structure also having anupper surface,

(iv) a first conductive silicide layer on said upper surface of saidbase layer, and the second conductive silicide layer on said uppersurface of said emitter structure, said first and second conductivesilicide layers not contacting each other,

said method comprising providing a narrow oxide spacer ring surroundingsaid sidewall of said emitter structure, said spacer ring being formedby chemical vapor deposition and anisotropic plasma etching, said firstconductive silicide layer surrounding said spacer ring, said methodfurther comprising applying a voltage pulse between said first andsecond conductive silicide layers to form a filament between said firstand second conductive layers, said filament extending from said secondconductive layer down said sidewall of said emitter structure and undersaid spacer ring to said second conductive layer.

In another aspect the invention provides an antifuse comprising:

(a) a silicided single polysilicon bipolar transistor structurecomprising:

(i) a collector layer,

(ii) a base layer overlying said collector layer and having an uppersurface,

(iii) an emitter structure overlying said base layer, said emitterstructure projecting above said base layer and having a sidewallextending above said base layer, said emitter structure also having anupper surface,

(iv) an oxide spacer ring surrounding said sidewall of said emitterstructure, said spacer ring being formed by chemical vapor depositionand anisotropic plasma etching and being of narrow and well definedthickness,

(v) a first conductive silicide layer on said upper surface of said baselayer, surrounding said spacer ring, and a second conductive silicidelayer on said upper surface of said emitter structure, said first andsecond conductive silicide layers not contacting each other,

(b) and a conductive filament extending between said first and secondconductive layers, said filament extending from said first conductivelayer down said sidewall of said emitter structure and under said spacerring to said second conductive layer.

In a third aspect the invention provides a method of making an antifusein a silicided double polysilicon bipolar transistor, said transistorcomprising:

(i) a collector, emitter and base, said collector being located besidesaid emitter and said emitter being located beside said base, each ofsaid collector, emitter and base having a lower portion,

(ii) the lower portion of said emitter having a sidewall,

(iii) the lower portion of said emitter including a first polysiliconlayer and a first conductive silicide layer, and the lower portion ofsaid base including a second polysilicon layer and a second conductivesilicided layer, said first and second conductive silicided layers notcontacting each other, said method comprising providing a narrow oxidespacer ring surrounding said sidewall of said lower portion of saidemitter, said spacer ring being formed by chemical vapor deposition andanisotropic plasma etching, said method further comprising applying avoltage pulse between said first and second conductive silicide layersto form a filament between said first and second conductive layers, saidfilament extending under said spacer ring.

In a fourth aspect the invention provides an antifuse comprising:

(a) a double silicided polysilicon bipolar transistor structurecomprising a collector, emitter and base, said collector being locatedbeside said emitter and said emitter being located beside said base,each of said collector, emitter and base having a lower portion,

(b) the lower portion of said emitter having a sidewall,

(c) the lower portion of said emitter including a first polysiliconlayer and a first conductive silicide layer, and the lower portion ofsaid base including a second polysilicon layer and a second conductivesilicide layer, said first and second conductive silicided layers notbeing in contact with each other,

(d) said emitter having an oxide spacer ring surrounding said sidewallof said lower portion of said emitter, said spacer ring being formed bychemical vapor deposition and anisotropic plasma etching and being ofnarrow and well defined thickness,

(e) and a conductive filament extending from said first conductivesilicide layer under said spacer ring to said second conductivesilicided layer.

Further objects and advantages of the invention will appear from thefollowing description, taken together with accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

In the drawings:

FIG. 1 is a cross-sectional view showing a prior art antifuse;

FIG. 2 is a graph showing the breakdown characteristic of the baseemitter diode of the FIG. 1 structure;

FIG. 3 is a cross-sectional view showing an antifuse according to theinvention, with the left side showing the structure before programmingand the right side showing the structure after programming;

FIG. 4 is a schematic showing the arrangement used to program antifusesof the invention;

FIG. 5A is a plot showing the voltage pulse applied to program theantifuse device of FIG. 2 and also showing the voltage at the input ofthe device;

FIG. 5B is a plot similar to that of FIG. 5A but showing voltagesapplied after the device has been programmed;

FIG. 6 shows the distribution of the emitter-base breakdown voltages fora set of functional discrete transistors of the kind shown in FIG. 2,before programming;

FIG. 7 shows the impedances of the devices referred to in connectionwith FIG. 6, after programming;

FIG. 8 shows the entire population of the sample programmed;

FIG. 9 shows the mean impedance after programming at a range of biascurrents; and

FIG. 10 is a cross-sectional view showing the invention as applied to adouble polysilicon bipolar transistor.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENT

Reference is first made to FIG. 1, which shows a planar diffused bipolartransistor 10 of the kind shown in U.S. Pat. No. 3,191,151, and having acollector 12, a base 14 and an emitter 16. When reverse biased, thebase-emitter junction 18 serves as an approximation to an electricalopen circuit, thereby constituting the OFF state of the antifuse.

When a large reverse bias is applied to the base emitter junction 18,electrical breakdown occurs as shown in FIG. 2. In FIG. 2, which plotsbase current against base-emitter voltage, the normal reverse leakagecurrent under reverse bias is indicated at 20. When the base-emittervoltage becomes high enough, electrical breakdown occurs, as indicatedat 22. As the electrical breakdown continues, heating occurs, causing asecondary thermal breakdown during which part of the base-emitterjunction 18 melts. The metal 24, 26 contacting the base and emitterregions then diffuses into the molten region, causing effectively ashort circuit so that the voltage across the junction drops and thecurrent rises, as indicated by region 28 in FIG. 2. Upon solidificationof the molten region, a metal filament indicated by arrow 30 (FIG. 1) isformed between the metallic base and emitter contacts 24, 26. Thefilament serves as an approximation to an electrical short, andconstitutes the ON state of the antifuse. This is indicated by region 31of FIG. 2.

A problem with the transistor 10 shown in FIG. 1 used as an antifuse, isthat the transistor 10 is formed primarily by lithographic steps, theaccuracy of which is inherently limited. For example, the base 14 andemitter 16 are superimposed on the collector 12, and the oxide layers 32a, 32 b are formed, all through the use of lithographic steps. There arenatural limits to the precision of these steps. Therefore, in practice,the total length of the metal filament indicated by arrow 30 istypically between 4 and 5 microns. The voltage, current and total energyrequired to create a filament of this length are relatively high,resulting in the potential for damage to surrounding circuit elements.

In a preferred embodiment of the invention, the base emitter junction ofa silicided single polysilicon bipolar transistor 40 (FIG. 3) is used asan antifuse. As will be discussed, this arrangement allows the distancebetween the metals on the base and emitter regions to be reduced byapproximately a factor of five, and this distance is better controlledsince it is defined by self aligned processing steps. The shorterdistance between the base and emitter metals in the silicided singlepolysilicon bipolar transistor 40 serves to lower the applied voltageand energy required to switch the antifuse from its OFF state to its ONstate by a factor of approximately two, as compared to a planar diffusedbipolar transistor. As mentioned, the lower programming voltage is asubstantial advantage, because in the process of programming theantifuse, the surrounding circuitry is much less likely to be damaged.

In a preferred embodiment, the transistor 40 is constructed as follows.Firstly, the base region 42 (shown as a P-type region but the types canbe reversed) is implanted into an n-eipitaxial or n-well region 44 ofmonosilicon. Next, n-type polysilicon is deposited and patterned on topof the base region 42 to form the emitter 46. These steps are, as usual,lithographic steps.

Next, a layer of silicon dioxide (not shown) is deposited by chemicalvapor deposition and is then subjected to anisotropic plasma etching,resulting in a ring-shaped sidewall oxide spacer 50 encircling thesidewall 52 of the emitter 46. It is a well known feature of anisotropicetching of an oxide layer (as shown by U.S. Pat. No. 5,019,878) that thethinner portions of the oxide layer are removed during the etchingprocess, but that an oxide ring remains from the thicker portion where afeature projects above the surrounding surface. The radial dimensions ofthe sidewall ring 50 (as shown by dimension “r” in FIG. 3) are welldefined by the process step and are not defined by a lithographic step.

Next, the exposed emitter polysilicon 46, and the base silicon 42 (whichas mentioned is monocrystalline silicon) are silicided by depositing oneof the following metals at elevated temperature: Co, Mo, Ni, Pt, Ta, Tior W (Pt is shown as an example). Such siliciding is well known in theart. At elevated temperatures, these metals react with all exposedsilicon to form a silicide, but they do not react with the silicondioxide layer or sidewall ring 50. Consequently, etchants can be used toremove the unreacted metal and leave the silicide in place. By thisprocess, the transistor 40 shown in FIG. 3 is fabricated.

As shown, the transistor 40 in FIG. 3 now has a low resistivity contact(e.g. of platinum silicide) 56 on the emitter 46, and a surrounding lowresistivity contact layer 58 (e.g. of platinum silicide) on the base 42,with only a short distance between these two contacts, defined by theoxide ring or sidewall spacer 50.

When a controlled programming voltage is applied between the contacts56, 58, electrical and then thermal breakdown occur between the base 42and the emitter 46, causing a silicide filament 60 (e.g. platinumsilicide) to grow. Typically the height or dimension “d” of the sidewalloxide spacer 50 is about 0.4 microns, and its thickness in the radialdimension “r” is about 0.25 microns, so the total length of the filament60 is about 0.65 microns, while its width is typically about 0.35microns. This length (0.65 microns) is far less than the length of thefilament required in a conventional bipolar transistor, and thereforerequires less energy to produce.

A simple circuit used to program antifuses of the invention is shown inFIG. 4. As shown, firstly a measuring instrument 64 is connected totransistor 40 (drawn for convenience as a zener diode) to measure theemitter-base breakdown voltage of transistor 40. Next, a voltage pulsewas applied from voltage supply 66 through a 250 ohm current limitingresistor 68 to the emitter-base junction. In the specific transistors 40used, it was found that the breakdown voltage was approximately 5 volts(this varied slightly from device to device), and that a voltage pulseof 9 volts superimposed on the breakdown voltage (total approximately 14volts) was optimum for producing the filament 60.

FIG. 5A shows a plot of the voltage pulse versus time used to form theantifuse (i.e. the filament 60). The top trace 70 shows the pulseapplied by the voltage source 66 at terminal A of the current limitingresistor 68. The bottom trace 72 shows the voltage at the input terminal58 of the device, namely the emitter-base voltage. The voltage pulse wasof about 5 milliseconds duration, with a rise time (shown by curveportion 74) of approximately 150 microseconds. It will be seen from theportion 74 of plots 70, 72 that the entire antifuse process (theformation of the filament 60) occurs within the short rise time of thepulse 70.

FIG. 5B shows the same pulse applied to the device 40 after formation ofthe antifuse. The top trace 78 shows the voltage pulse applied to thetop terminal A, while the lower trace 80 shows the voltage pulse appliedto the emitter 58, i.e. the emitter-base voltage. It will be seen thatno further changes to the junction are observed from this pulse, i.e.the filament 60 has already been formed and no further filaments areformed.

FIG. 6 displays a curve 82 showing the emitter-base breakdown voltagedistribution for a number of functional discrete transistors 40 beforethe filament forming voltage pulse 74 was applied. It will be seen thatthe mean emitter-base breakdown voltage was approximately 5 volts, butthat there was (as would be expected) a fairly substantial variationfrom this level. The voltage pulse applied was, as mentioned, 9 voltsplus the measured emitter-base breakdown voltage.

After formation of the filaments 60 on a number of devices 40, voltagemeasurements of the collector/emitter-base junctions were made at biascurrent levels of 50, 100, 150 and 200 microamperes, and impedances werecalculated. FIG. 7 shows the data for the impedances at a 50 microamperebias current with the number of devices plotted on the vertical axis andthe impedance on the horizontal axis. Curve 84 plots the average of theimpedances found. The mean impedance was approximately 73 ohms with astandard deviation of 16 ohms. This was a relatively low impedance,bearing in mind that the impedance before formation of the filament 60was nearly that of an open circuit.

FIG. 8 shows the entire population of the sample shown in FIG. 7. Thenumber of devices appears on the vertical axis and the impedance on thehorizontal axis. It will be seen that there are three outlying devices90, 92 and 94 between 600 and 800 ohms. This indicates that a smallpercentage of the devices subjected to the filament forming voltagepulse will exhibit a partial antifuse characteristic. This appeared toindicate process flaws or structural differences in the transistors inquestion and is indicative of some yield loss during production, in thesamples tested.

FIG. 9 plots at 100 the mean impedance (on the vertical axis) at eachbias current (on the horizontal axis) for typical devices after theantifuse filament 60 was formed. It will be seen that the impedancedrops from 72.9 ohms at 50 microamps bias current to 70.9 ohms at 200microampere bias current. This relatively small variation does not causedifficulty in use.

With the devices tested, it was found that pulses of less than 12 voltstotal (reverse breakdown voltage of 5 volts plus a 7 volt pulsesuperimposed) were not sufficient to create the antifuse filament, whilepulses greater than about 15 volts total (5 volts breakdown voltage plus10 volts superimposed) tended to create junctions having much higherresistances (more than 300 ohms and increasing with voltage). Asmentioned, pulses of approximately 14 volts (9 volts plus the breakdownvoltage) were ideal.

It was also found that the average energy during the rise time part ofthe pulse, where the filament was actively formed, was approximately 6.6microjoules. Thus, it will be seen that only a relatively small amountof energy is needed to program the devices.

In some tests, a rise time of less than one-tenth the rise timedisclosed (approximately 12 microseconds instead of 150 microseconds)was used, and the antifuses produced tended to have higher impedancesand a broader distribution of impedances. It is not known at the presenttime whether the longer rise time of the voltage pulses used wasbeneficial in forming the antifuse filaments 60, but it is suspectedthat the relatively slow rise time may have been beneficial since itallowed the filaments 60 an optimal time to form.

While a single polysilicon bipolar transistor has been described, ifdesired the invention may also be applied to a double polysiliconbipolar transistor. Such a transistor is shown at 110 in FIG. 10 andincludes base, emitter and collector metal contacts 112, 114, 116, 120and 122, respectively. The transistor 110 also includes amonocrystalline extrinsic base 124 (of p material), and conventionalsilicon dioxide layers 126, 128 on a substrate 130. (Layers 126, 128 arethe interlayer dielectric and field oxide layers respectively.) Anencircling trench 132, filled with polysilicon 134, helps to provideelectrical isolation from neighbouring devices. The transistor 110 as sofar described is conventional.

As in the single polysilicon bipolar transistor 40 previously described,when the transistor 110 is being formed, and after the polysiliconlayers 118, 120 and 122 are deposited, these layers are silicided bydepositing (e.g. by sputtering) a layer of metal (e.g. platinum) overthe surface of the wafer at elevated temperatures, thus forming asilicide with the exposed silicon but not with the silicon dioxide layerwhich is exposed. The wafer is then treated with an agent (e.g. a strongacid) to remove the unreacted metal, leaving the silicided layers whichare shown at 136, 138 and 140.

It is also noted that during the process of forming the transistor, andduring the depositing and etching of the silicon dioxide, a ring-shapedsidewall oxide spacer 142 is formed, encircling a sidewall of theemitter polycrystalline 120 (exactly as in the FIG. 3 arrangement).Since the radial dimensions of the sidewall spacer or ring 142 aredefined by a process step (anisotropic etching) and not by alithographic step, these dimensions are (as previously mentioned) verywell defined.

Thus, when a controlled programming voltage is applied between the baseand emitter contacts 112, 114, electrical and then thermal breakdownoccur between the base and the emitter, causing a silicide filament 146(a metal silicide, e.g. platinum silicide) to grow. The filament 146 isof necessity longer than the silicide filament 60 of FIG. 3, because ofthe need for the filament to grow through a number of layers, namely,the emitter polysilicon layer 120, the monocrystalline silicon emitterlayer 148, the extrinsic base 124, and the base polysilicon 118.However, the filament 146 is still relatively short, typically of theorder of 1.0 micron in length. (This is because the difference betweenthe filament length for the single and double polysilicon bipolartransistors is the thickness of the base polysilicon, which is about0.35 microns thick. Thus the length of filament 146 is approximately0.65+0.35=1.0 micrometers.)

While the filament 146 is approximately 50% longer than the filament 60in the FIG. 3 version, it is nevertheless much shorter than in the priorart. While the voltage or current pulse needed to form the filament 146will be larger than those needed for the filament 60, again they will berelatively low and well defined.

While preferred embodiments of the invention have been described, itwill be realized that various changes may be made within the scope ofthe invention. For example a variety of semiconductors and metals can beused beyond those specified, and the region specified as p and n cantake on the opposite type if desired.

We claim:
 1. An antifuse comprising: (a) a silicided polysilicon bipolar transistor structure comprising a collector, base and emitter, said emitter having a sidewall and a narrow oxide spacer ring surrounding said sidewall, said base including a first polysilicon layer and said emitter including a second polysilicon layer, (b) and a conductive filament extending from said first conductive layer under said spacer ring to said second conductive layer.
 2. A device according to claim 1 wherein said transistor is a single polysilicon bipolar transistor.
 3. A device according to claim 2 wherein said filament is approximately 0.6 microns in length.
 4. A device according to claim 1 wherein said transistor is a double polysilicon bipolar transistor.
 5. A device according to claim 4 wherein said filament is approximately 1.0 micron in length.
 6. An antifuse comprising: (a) a silicided single polysilicon bipolar transistor structure comprising: (i) a collector layer, (ii) a base layer overlying said collector layer and having an upper surface, (iii) an emitter structure overlying said base layer, said emitter structure projecting above said base layer and having a sidewall extending above said base layer, said emitter structure also having an upper surface, (iv) a narrow oxide spacer ring surrounding said side wall of said emitter structure, (v) a first conductive silicide layer on said upper surface of said base layer, surrounding said spacer ring, and a second conductive silicide layer on said upper surface of said emitter structure, (b) and a conductive filament extending between said first and second conductive layers, said filament extending from said first conductive layer down said sidewall of said emitter structure and under said spacer ring to said second conductive layer.
 7. A device according to claim 6 wherein said oxide ring is approximately 0.25 microns in width.
 8. A device according to claim 7 wherein said filament is approximately 0.65 microns in length.
 9. A device according to claim 8 wherein said filament is approximately 0.35 microns in width. 